The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of lightly doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Typically, the structural and doping parameters tending to provide a desired increase in drive current adversely impact leakage current.
Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high temperature annealing to activate the source/drain implants, as at a temperature in excess of 900° C. This fabrication technique may degrade the metal gate electrode or cause interaction with the gate dielectric, thereby adversely impacting transistor performance.
Replacement gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes, for high performance logic for 28 nanometer (nm) technologies and beyond. For example, a polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the polysilicon is removed and replaced with a metal gate.
In stand-alone dynamic random-access memories (DRAMs), recessed channel transistors, e.g., u-shaped or saddle shaped 3d-transistors, have been employed for their superior retention behavior. The recessed channel creates an enlarged effective channel length, which in turn improves the relationship between off-state channel leakage (loff) and gate-induced drain leakage current. The reduced leakage current corresponds to the static and dynamic retention characteristics of a DRAM chip, providing longer retention time than a conventional local-damascene FinFET.
Embedded DRAMs, or eDRAMs, integrate memory and logic on a single chip. Since eDRAMs reduce both total chip count in a system and also power consumption while increasing performance, they are particularly useful for system-on-chip (SoC) designs, which may additionally include other types of transistors, such as high voltage transistors. However, the recessed channel transistors used for DRAMs and the replacement gate transistors used for high performance logic are formed by different processes.
A need therefore exists for methodology enabling combining high performance logic transistor technology and ultra low leakage DRAM transistor technology for embedded DRAM or system-on-chip (SoC), and the resulting device.